P3 CPU Assembly Format

The P3 has 7 general purpose registers, R0-R7 (R0 is always 0x0000, cannot be changed).

Two more registers are available to the programmer, SP (stack pointer) and PC (program counter).

Addressing Modes

Code Name Operand
Rx, PC, SP Register A register.
M[Rx] Register Indirect A position in memory addressed by a register.
W Immediate A 16-bit constant.
M[W] Direct A position in memory addressed by a 16-bit constant.
M[Rx+W] Indexed A position in memory addressed by a register and a 16-bit constant.
M[PC+W] PC-Relative A position in memory addressed by PC and a 16-bit constant.
M[SP+W] SP-Relative A position in memory addressed by SP and a 16-bit constant.

Instructions

Operands Description
op, opX Operand
c4 Constant 4-bit
c6 Constant 6-bit
c10 Constant 10-bit
Instruction Operands Flags Action
NOP none   No operation.
ENI none E Enable interrupts.
DSI none E Disable interrupts.
STC none C Set the carry flag to 1.
CLC none C Set the carry flag to 0.
CMC none C Invert the carry flag.
RET none   Return from a routine.
RTI none EZCNO Return from an interrupt routine.
INT c10 EZCNO Trigger interrupt with interrupt vector c10, regardless of the E flag.
RETN c10   Return from a routine and free c10. positions from the stack.
NEG op ZCNO Invert the sign of op.
INC op ZCNO Increment op.
DEC op ZCNO Decrement op.
COM op ZN Bitwise NOT, complement (op = !op).
PUSH op   Push op to the top of the stack.
POP op   Pop the top of the stack to op.
SHR op, c4 ZCN Shift right op by c4 bits.
SHL op, c4 ZCN Shift left op by c4 bits.
SHRA op, c4 ZCNO Arithmetic shift right, same as SHR but sets the overflow flag.
SHLA op, c4 ZCNO Arithmetic shift left, same as SHL but sets the overflow flag.
ROR op, c4 ZCN Rotate right op by c4 bits.
ROL op, c4 ZCN Rotate left op by c4 bits.
RORC op, c4 ZCN Rotate right (with carry) op by c4 bits.
ROLC op, c4 ZCN Rotate left (with carry) op by c4 bits.
CMP op0, op1 ZCNO Compare op0 and op1 (same as SUB without changing any operands).
ADD op0, op1 ZCNO Add op0 and op1 (op0 = op0 + op1).
ADDC op0, op1 ZCNO Add op0, op1 and the carry flag (op0 = op0 + op1 + C).
SUB op0, op1 ZCNO Subtract op0 and op1 (op0 = op0 - op1).
SUBB op0, op1 ZCNO Subtract op0, op1 and the carry flag (op0 = op0 - op1 - C).
MUL op0, op1 ZCNO Multiply (no sign) op0 by op1, both operands are used to store the result (op0 | op1 = op0 * op1).
DIV op0, op1 ZCNO Divide (no sign) op0 by op1, both operands are used to store the result (op0 = result; op1 = remainder).
TEST op0, op1 ZN Test op0 and op1 (same as AND without changing any operands).
AND op0, op1 ZN Bitwise AND (op0 = op0 ∧ op1).
OR op0, op1 ZN Bitwise OR (op0 = op0 ∨ op1).
XOR op0, op1 ZN Bitwise XOR (op0 = op0 ⊕ op1).
MOV op0, op1   Copy op1 to op0 (op1 = op0).
MVBH op0, op1   Copy higher byte of op1 to the higher byte of op0 (op0 = (op0 and 0x00ff) or (op1 and 0x00ff)).
MVBL op0, op1   Copy lower byte of op1 to the lower byte of op0 (op0 = (op0 and 0xff00) or (op1 and 0xff00)).
XCH op0, op1   Exchange op0 and op1 (op0 = op1; op1 = op0)
JMP op   Unconditional jump to op.
JMP.cond op   Jump to op based on condition cond.
CALL op   Unconditional routine call to op.
CALL.cond op   Routine call to op based on condition cond.
BR c6   Unconditional branch jump to PC + c6.
BR.cond c6   Branch jump to PC + c6 based on condition cond.